RC4 Core [CVS]
This rc4 core is made to be fairly general purpose and was kind of my first attempt at implementing it. The core I'm using for pico-wepcrack is a lot more optimal for cracking wep specifically and could be adapted for whatever type of rc4 implementation you'd like to do, but I thought I'd keep this one up here just in case. The main feature of this one is that you can kick off rc4 at any point in the computation by setting the initial S-Box state to whatever you like and specifying the I and J start values for RC4. It is also designed to only compute the first 6 bytes of RC4, but can be easily adapted to do whatever length you like or to stream the bytes.
Pico-Wepcrack Core [CVS]
This rc4 core is specifically made to be small and to only compute the first 6 bytes of PRGA. The idea for this core is to have a higher level core that feeds it possible WEP keys and then verifies if the key is correct by seeing if the PRGA ^ packet0 == [the first 6 bytes of the snap header]. The main difference between this core and the previous is that it uses a 16-bit BlockRAM for the S-Box and swaps between using the top 8 bits and the bottom 8 bits for KSA/PRGA and for Initialization, which allows you to skip the Initialization step when running rc4 continuously back-to-back (this is explained a bit better in my LayerOne and RECON presentations). Airbase (jc-wepcrack) currently has basic Pico E-12 acceleration support, for more information on Airbase, check out the link below.
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