SHA-1 Core

This core is a tiny implementation of SHA-1 that is optimized more for size than speed. It requires less than 500 Slices and 4 BlockRAMs and can be clocked up to 120MHz on the Virtex-4 (80 clock cycles are required for valid data). It uses a simple bus interface to write values to it and pull out results. The end goal of this project is to create a full core that is able to accelerate WPA-PSK cracking through hooks into coWPAtty and/or aircrack. The small size should allow us to parallelize multiple instances of the SHA-1 core on an FPGA to multiply the performance.


This is the SHA1 core adapted for doing WPA-PSK cracking. It uses BlockRAMs to buffer the SHA1 input and output values to streamline throughput. It's setup to accomodate larger FPGA designs that can use more SHA1 cores to increase performance.


Currently coWPAtty has full support for cracking WPA-PSK on the Pico E-12 card. This project contains the modifications made to coWPAtty and the proper Pico E-12 bit file to use FPGA acceleration under Linux 2.4 using the pcmcia-cs memory_cs driver. The FPGA acceleration provides roughly a 6x speed improvement over a top of the line Intel/AMD processor as shown below:

800MHz P3
3.6GHz+ P4
2.16GHz Intel Duo

Pico E-12 (Virtex-4 LX25)
Pico E-14 (Virtex-4 FX20)
Pico E-14 (Virtex-4 FX60)

Precomputed Hashtables

The Shmoo Group has been nice enough to host our WPA tables on their bittorrent tracker located here. If you want to help out, please download and seed the tables to help speed up the download for others.

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